Phase locked loops are commonly used to derive from a serial data signal a clock that is to be used for sampling and other processing of the data signal. An example of such a use is given in U.S. Pat. No. 4,908,841 issued Mar. 13, 1990 to Leis et al, entitled "Data Decoding Circuit Including Phase-Locked Loop Timing".
In many applications, including data storage applications such as described in the Leis patent, the data stream is intermittent rather than continuous. This intermittent nature of the data places special demands on the phase locked loop. Whenever a new burst of data is received, such as after a seek or head switch in a data storage device, the system must wait for the phase locked loop to acquire phase lock before the data can be sampled. This of course has the effect of increasing data latency. Phase locked loop acquisition time is therefore an important factor affecting system performance.
In addition, phase lock acquisition occurs when a special magnetic pattern called a preamble is passing under the readback head in the data storage device. A longer acquisition time demands a longer preamble stored on the medium, reducing the amount of space available for user data.
It is therefore desirable to minimize phase locked loop acquisition time for performance and capacity reasons. However, it is known that phase locked loops can exhibit unacceptably long acquisition times, and even fail to lock within a predetermined maximum time under some circumstances. The nature of these problems is described in an article by Floyd M. Gardner entitled "Hangup in Phase-Lock Loops", IEEE Transactions on Communications, Vol. COM-25, No. 10, October 1977. This article points out that acquisition may start around a "reverse-slope null", i.e., a point where the initial phase difference is halfway between two stable phase-locked operating points. In such cases, acquisition may take numerous cycles. And as Gardner points out, the presence of noise in the data signal can actually exacerbate these problems.
A general technique used to avoid long acquisition time is to apply a large initial correction to the voltage-controlled oscillator (VCO) to rapidly bring its phase close to that of the data signal. Subsequent phase locking presumably then proceeds more rapidly; also, the reverse-slope null is avoided. The amount of correction to be applied is determined by sampling the data-to-clock phase difference at the beginning of acquisition. The above-referenced Gardner article describes a scheme employing this general idea.
A variation of this scheme, commonly called "zero-phase start", has been widely used in digital phase locked loops. In this approach, the initial data-to-clock phase difference is measured, and the result is used to stop the VCO for sufficient time to correct for this phase difference. Examples of this scheme can be found in U.S. Pat. No. 5,170,297 issued Dec. 8, 1992 to Wahler et al., entitled "Current Averaging Data Separator", and U.S. Pat. No. 4,560,950 issued Dec. 24, 1985 to Cabot, entitled "Method and Circuit for Phase Lock Loop Initialization".
While these zero phase start schemes improve the acquisition times of their associated phase locked loops, they nevertheless suffer from one of the very problems giving rise to their use, namely noise. Noise appearing on the data signal can contribute to an inaccurate initial measurement. This of course could result in an inaccurate initial phase correction, and may actually increase rather than decrease acquisition time. In fact, there is a particular type of noise, commonly called "pulse pairing" noise in data storage systems, that limits the effectiveness of these zero phase start schemes. When pulse pairing occurs, adjacent pulses have alternating early/late phase errors. However, conventional zero phase start schemes that rely on a single initial measurement do not detect or compensate for such correlated noise.